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products and specifications discussed herein ar e subject to change by micron without notice. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm features pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 1 ?2003 micron technology, inc. all rights reserved. ddr sdram udimm mt8vddt3264a ? 256mb mt8vddt6464a ? 512mb for component data sheets, refer to micron?s web site: www.micron.com features ? 184-pin, unbuffered dual in-line memory module (udimm) ? fast data transfer rates: pc2100, pc2700, or pc3200 ? 256mb (32 meg x 64), and 512mb (64 meg x 64) ?v dd = v dd q = +2.5v (-40b: v dd = v dd q) ?v ddspd = +2.3v to +3.6v ? 2.5v i/o (sstl_2-compatible) ? internal pipelined double data rate (ddr) 2 n -prefetch architecture ? bidirectional data strobe (dqs) transmitted/ received with data?that is, source-synchronous data capture ? differential clock inputs (ck and ck#) ? multiple internal device banks for concurrent operation ? single rank ? selectable burst lengths (bl): 2, 4, or 8 ? auto precharge option ? auto refresh and self refresh modes: 7.8125s maximum average periodic refresh interval ? serial presence-det ect (spd) with eeprom ? selectable cas latency (cl) for maximum compatibility ? gold edge contacts 184-pin udimm (mo-206) figures figure 1: standard layout p c b hei g ht: 31.75mm (1.25in) figure 2: alternative layout figure 3: redu ced-height layout notes: 1. contact micron for industrial temperature module offerings. 2. not recommended for new designs. options marking ? operating temperature 1 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 184-pin dimm (standard) g ? 184-pin dimm (pb-free) y ? memory clock, speed, cas latency ? 5.0ns (200 mhz), 400 mt/s, cl = 3 -40b ? 6.0ns (167 mhz), 333 mt/s, cl = 2.5 -335 ? 7.5ns (133 mhz), 266 mt/s, cl = 2 2 -262 ? 7.5ns (133 mhz), 266 mt/s, cl = 2 2 -26a ? 7.5ns (133 mhz), 266 mt/s, cl = 2.5 2 -265 p c b hei g ht: 31.75mm (1.25in) p c b hei g ht: 28.58mm (1.125in)
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 2 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm features notes: 1. the values of t rcd and t rp for -335 modules show 18ns to a lign with industry specifications; actual ddr sdram device specifications are 15ns. notes: 1. data sheets for the base device s can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factor y for current revision codes. example: mt8vddt3264ay-335g6 . table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) notes cl = 3 cl = 2.5 cl = 2 -40b pc3200 400 333 266 15 15 55 -335 pc2700 ? 333 266 18 18 60 1 -262 pc2100 ? 266 266 15 15 60 -26a pc2100 ? 266 266 20 20 65 -265 pc2100 ? 266 200 20 20 65 table 2: addressing parameter 256mb 512mb refresh count 8k 8k row address 8k (a0?a12) 8k (a0?a12) device bank address 4 (ba0, ba1) 4 (ba0, ba1) device configuration 256mb (32 meg x 8) 512mb (64 meg x 8) column address 1k (a0?a9) 2k (a0?a9, a11) module rank address 1 (s0#) 1 (s0#) table 3: part numbers and timing parameters ? 256mb base device: mt46v32m8, 1 256mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8vddt3264ag-40b__ 256mb 32 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt3264ay-40b__ 256mb 32 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt3264ag-335__ 256mb 32 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt3264ay-335__ 256mb 32 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt3264ag-262__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt8vddt3264ag-26a__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt3264ag-265__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt3264ay-265__ 256mb 32 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 table 4: part numbers and timing parameters ? 512mb base device: mt46v64m8, 1 512mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8vddt6464ag-40b__ 512mb 64 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt6464ay-40b__ 512mb 64 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt8vddt6464ag-335__ 512mb 64 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt6464ay-335__ 512mb 64 meg x 64 2.7 gb/s 6.0ns/333 mt/s 2.5-3-3 mt8vddt6464ag-262__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt8vddt6464ag-26a__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt6464ag-265__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt6464ay-265__ 512mb 64 meg x 64 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 3 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm pin assignments and descriptions pin assignments and descriptions table 5: pin assignments 184-pin ddr udimm front 184-pin ddr udimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dnu 70 v dd 93 v ss 116 v ss 139 v ss 162 dq47 2 dq0 25 dqs2 48 a0 71 nc 94 dq4 117 dq21 140 dnu 163 nc 3v ss 26 v ss 49 dnu 72 dq48 95 dq5 118 a11 141 a10 164 v dd q 4 dq1 27 a9 50 v ss 73 dq49 96 v dd q 119 dm2 142 dnu 165 dq52 5 dqs0 28 dq18 51 dnu 74 v ss 97 dm0 120 v dd 143 v dd q 166 dq53 6 dq2 29 a7 52 ba1 75 ck2# 98 dq6 121 dq22 144 dnu 167 nc 7v dd 30 v dd q 53 dq32 76 ck2 99 dq7 122 a8 145 v ss 168 v dd 8 dq3 31 dq19 54 v dd q77v dd q100 v ss 123 dq23 146 dq36 169 dm6 9 nc 32 a5 55 dq33 78 dqs6 101 nc 124 v ss 147 dq37 170 dq54 10 nc 33 dq24 56 dqs4 79 dq50 102 nc 125 a6 148 v dd 171 dq55 11 v ss 34 v ss 57 dq34 80 dq51 103 nc 126 dq28 149 dm4 172 v dd q 12 dq8 35 dq25 58 v ss 81 v ss 104 v dd q 127 dq29 150 dq38 173 nc 13 dq9 36 dqs3 59 ba0 82 nc 105 dq12 128 v dd q 151 dq39 174 dq60 14 dqs1 37 a4 60 dq35 83 dq56 106 dq13 129 dm3 152 v ss 175 dq61 15 v dd q38 v dd 61 dq40 84 dq57 107 dm1 130 a3 153 dq44 176 v ss 16 ck1 39 dq26 62 v dd q85 v dd 108 v dd 131 dq30 154 ras# 177 dm7 17 ck1# 40 dq27 63 we# 86 dqs7 109 dq14 132 v ss 155 dq45 178 dq62 18 v ss 41 a2 64 dq41 87 dq58 110 dq15 133 dq31 156 v dd q 179 dq63 19 dq10 42 v ss 65 cas# 88 dq59 111 nc 134 dnu 157 s0# 180 v dd q 20 dq11 43 a1 66 v ss 89 v ss 112 v dd q 135 dnu 158 nc 181 sa0 21 cke0 44 dnu 67 dqs5 90 nc 113 nc 136 v dd q 159 dm5 182 sa1 22 v dd q 45 dnu 68 dq42 91 sda 114 dq20 137 ck0 160 v ss 183 sa2 23 dq16 46 v dd 69 dq43 92 scl 115 a12 138 ck0# 161 dq46 184 v ddspd
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 4 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm pin assignments and descriptions table 6: pin descriptions symbol type description a0?a12 input (sstl_18) address inputs: provide the row address fo r active commands, and the column address and auto precharge bi t (a10) for read/write commands, to select one location out of the memory a rray in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, devi ce bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0, ba 1 define which mode register (mode register or extended mode register ) is loaded during the load mode register command. ba0, ba1 input (sstl_18) bank address: ba0, ba1 define to which device bank an active, read, write, or precharge command is being applied. ck0, ck0#, ck1, ck1#, ck2, ck2# input (sstl_18) clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on th e crossing of the positi ve edge of ck and the negative edge of ck#. output data (dq and dqs) is referenced to the crossings of ck and ck#. cke0 input (sstl_18) clock enable: cke (registered high) activates and cke (registered low) deactivates the internal clock, in put buffers, and output drivers. dm0?dm7 input (sstl_18) input data mask: dm is an input ma sk signal for write data. input data is masked when dm is sampled high, alon g with that input data, during a write access. dm is sampled on both edges of dqs. although dm pins are input- only, the dm loading is designed to match that of dq and dqs pins. ras#, cas#, we# input (sstl_18) command inputs: ras#, cas#, and we# (alo ng with s#) define the command being entered. s0# input (sstl_18) chip selects: s# enables (registered low) and disables (registered high) the command decoder. sa0?sa2 input (sstl_18) presence-detect address inputs: these pins are used to configure the presence-detect device. scl input (sstl_18) serial clock for presence-detect: scl is used to synchronize the presence- detect data transfer to and from the module. dq0?dq63 i/o (sstl_18) data input/output: data bus. dqs0?dqs7 i/o (sstl_18) data strobe: output with read data, input with write data. dqs is edge- aligned with read data, center-aligned wi th write data. used to capture data. sda i/o (sstl_18) serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. v dd /v dd q supply power supply: +2.5v 0.2v (-40b: +2.6v 0.1v) v ddspd supply serial eeprom positive power supply: +2.3v to +3.6v. v ref supply sstl_2 reference voltage (v dd /2). v ss supply ground. dnu ? do not use: these pins are not connected on these modules, but are assigned on other modules in this product family. nc ? no connect: these pins are not connected on the module.
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 5 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm functional block diagrams functional block diagrams figure 4: functional block diagram ? standard layout u4, u6 ck0 ck0# u1?u3 ck1 ck1# u7?u9 ck2 ck2# a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp u10 v ref v ss ddr sdram ddr sdram v ddspd spd eeprom ddr sdram v ss dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u9 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u7 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u6 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s0# u3 dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm0 dm cs# dqs u8 dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dqs1 dm1 dqs2 dm2 dqs3 dm3 dqs4 dm4 dqs5 dm5 dqs6 dm6 dqs7 dm7 ba0, ba1 a0?a11/a12 ras# cas# we# cke0 ba0, ba1: ddr sdram a0?a11/a12: ddr sdram ras#: ddr sdram cas#: ddr sdram we#: ddr sdram cke0: ddr sdram v dd /v dd q
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 6 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm functional block diagrams figure 5: functional block diagram ? alternative and reduced-height layout ba0, ba1 a0?a11/a12 ras# cas# we# cke0 ba0, ba1: ddr sdram a0?a11/a12: ddr sdram ras#: ddr sdram cas#: ddr sdram we#: ddr sdram cke0: ddr sdram dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u5 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s0# u3 dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm0 dm cs# dqs u7 dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs ck0 ck0# u1?u4 ck1 ck1# u5?u8 ck2 ck2# dqs1 dm1 dqs2 dm2 dqs3 dm3 dqs4 dm4 dqs5 dm5 dqs6 dm6 dqs7 dm7 a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp u9 v ss ddr sdram ddr sdram spd eeprom ddr sdram u4, u5 ck0 ck0# u1?u3 ck1 ck1# u6?u8 ck2 ck2# reduced-height layout (28.58mm) pc b: alternative layout (31.75mm) pcb: v ref v ss v ddspd v dd /v dd q
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 7 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm general description general description the mt8vddt3264a, and mt8vddt6464a are high-speed, cmos, dynamic random access, 256mb, and 512mb memory modules organized in a x64 configuration. these modules use ddr sdram devices with four internal banks. ddr sdram modules use a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for ddr sdram modu les effectively consists of a single 2 n -bit- wide, one-clock-cycle data transfer at the internal dram core and two corresponding n - bit-wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-d etect operation ddr sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are progra mmed by micron to identify the module type and various ddr sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by th e customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight unique dimm/eeprom addr esses. write protect (wp) is connected to v ss , permanently disabling hardware write protect.
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 8 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm electrical specifications electrical specifications stresses greater than those listed in ta ble 7 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. for further information, refer to technical note tn-00-08: ?thermal applications ,? available on micron?s web site. table 7: absolute maximum ratings symbol parameter min max units v dd /v dd q v dd /v dd q supply voltage relative to v ss ?1.0 +3.6 v v in , v out voltage on any pin relative to v ss ?0.5 +3.2 v i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 1.35v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, ba, s#, cke ?16 +16 a ck0, ck0# (standard and alternative layouts) ?4 +4 ck1, ck1#, ck2, ck2# (standard and alternative layouts) ?6 +6 ck1, ck1#, ck2, ck2# (reduced-height layouts) ?8 +8 dm ?2 +2 i oz output leakage current; 0v v out v dd q; dqs are disabled dq, dqs ?5 +5 a t a dram ambient operating temperature 1 commercial 0+70c industrial ?40 +85 c
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 9 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate th e signal characteristics of the system?s memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 8: module and component speed grades ddr components may exceed th e listed module speed grades module speed grade component speed grade -40b -5b -335 -6 -262 -75e -26a -75z -265 -75
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 10 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm electrical specifications i dd specifications ta bl e 9 : i dd specifications and conditions ? 256mb (die revision ?k?) values are shown for the mt46v32m8 ddr sdram only and are computed from values specified in the 256mb (32 meg x 8) component data sheet parameter/condition symbol -40b -335 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 800 720 ma operating one bank active-read-precharge current: bl = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 960 920 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low i dd 2p 32 32 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once pe r clock cycle; v in =v ref for dq, dm, and dqs i dd 2f 400 400 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 280 240 ma active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 480 440 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out =0ma i dd 4r 1,440 1,280 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 1,440 1,280 ma auto refresh current t refc = t rc (min) i dd 5 1,280 1,280 ma t refc = 7.8125s i dd 5a 48 48 ma self refresh current: cke 0.2v i dd 63232ma operating bank interleave read current: four device bank interleaving reads; bl = 4 with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 2,320 2,160 ma
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 11 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm electrical specifications table 10: i dd specifications and conditions ? 256mb (all other die revisions) values are shown for the mt46v32m 8 ddr sdram only and are computed from values specified in the 256mb (32 meg x 8) component data sheet parameter/condition symbol -40b -335 -262 -26a/ -265 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1,080 1,000 1,000 960 ma operating one bank active-read-precharge current: bl = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 1,360 1,360 1,280 1,160 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low i dd 2p 32 32 32 32 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dm, and dqs i dd 2f 480 400 360 360 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 320 240 200 200/ 240 ma active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 560 480 400 400 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and co ntrol inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 1,600 1,400 1,200 1,200 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address an d control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 1,560 1,400 1,200 1,200 ma auto refresh current t refc = t rc (min) i dd 5 2,080 2,040 1,880 1,880/ 1,960 ma t refc = 7.8125s i dd 5a 48 48 48 48 ma self refresh current: cke 0.2v i dd 632323232ma operating bank interleave read current: four device bank interleaving reads; bl = 4 with auto precharge: t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 3,760 3,280 2,800 2,800/ 2,920 ma
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 12 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm electrical specifications table 11: i dd specifications and conditions ? 512mb values are shown for the mt46v64m 8 ddr sdram only and are computed from values specified in the 512mb (64 meg x 8) component data sheet parameter/condition symbol -40b -335 -262 -26a/ -265 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1,240 1,040 1,040 920 ma operating one bank active-read-precharge current: active-read precharge; bl = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 1,480 1,280 1,280 1,160 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low i dd 2p 40 40 40 40 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dm, and dqs i dd 2f 440 360 360 320 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 360 280 280 240 ma active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 480 400 400 360 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and co ntrol inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 1,520 1,320 1,320 1,160 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address an d control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 1,560 1,400 1,240 1,080 ma auto refresh current t refc = t rc (min) i dd 5 2,760 2,320 2,320 2,240 ma t refc = 7.8125s i dd 5a 88 80 80 80 ma self refresh current: cke 0.2v i dd 640404040ma operating bank interleave read current: four device bank interleaving reads; bl = 4 with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 3,600 3,240 3,200 2,800 ma
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 13 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detect data, refer to micron's spd page: www.micron.com/spd . table 12: serial presence-detec t eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?1.0 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?30a power supply current: scl clock frequency = 100 khz i cc ?2.0ma table 13: serial presence-detec t eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns clock/data fall time t f ? 300 ns 2 clock/data rise time t r ? 300 ns 2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 14 ?2003 micron technology, inc. all rights reserved. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm module dimensions module dimensions figure 6: 184-pin udimm ? standard layout notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. u1 u2 u3 u4 u6 u7 u8 u9 u10 no components this side of module front view back view 1.37 (0.054) 1.17 (0.046) 3.18 (0.125) max pin 1 17.78 (0.7) typ 2.5 (0.098) d (2x) 2.3 (0.091) typ 6.35 (0.25) typ 1.27 (0.05) typ 2.21 (0.087) typ 1.02 (0.04) typ 2.0 (0.079) r (4x) 0.9 (0.035) r pin 92 133.50 (5.256) 133.20 (5.244) 64.77 (2.55) typ 49.53 (1.95) typ pin 184 pin 93 10.0 (0.394) typ 1.0 (0.039) typ 2.92 (0.115) typ 73.41 (2.89) typ 31.88 (1.255) 31.62 (1.245) 120.65 (4.75) typ
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits spec ified over the power supply an d temperature range set forth herein. although considered final, these specifications ar e subject to change, as furthe r product development and data characterization sometimes occur. 256mb, 512mb (x64, sr) 184-pin ddr sdram udimm module dimensions pdf: 09005aef80867ab3/source: 09005aef80867a99 micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x64a.fm - rev. j 8/08 en 15 ?2003 micron technology, inc. all rights reserved. figure 7: 184-pin udimm ? alternative and reduced-height layout notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. 28.7 (1.13) 28.45 (1.12) pin 1 17.78 (0.7) typ 2.5 (0.098) d (2x) 2.31 (0.091) typ 6.35 (0.25) typ 120.65 (4.75) typ 1.27 (0.05) typ 2.21 (0.87) typ 1.02 (0.04) typ 2.0 (0.079) r (4x) 0.035 (0.9) r pin 92 front view back view 1.37 (0.054) 1.17 (0.046) 133.50 (5.256) 133.20 (5.244) 64.77 (2.55) typ 49.53 (1.95) typ pin 184 pin 93 10.0 (0.394) typ 3.18 (1.125) max u1 u2 u3 u4 u5 u6 u7 u8 u9 no components on this side of module 1.0 (0.039) typ 2.92 (0.115) typ 73.41 (2.89) typ

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